Semiconductor device with selectable gate thickness and method of manufacturing such devices
US6855605B2 · kind B2 · utility
20Cited by
9References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2002 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Apr 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0179
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts can be formed by doping the selected regions to the desired depth d. The as-deposited thickness t of this device layer can be adjusted or modulated after the patterning of the individual devices by removing the disposable parts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.