Inventor · Montbonnot-Saint-Martin, FR

Emmanuel Augendre

31Patents

4h-index

34Co-inventors

63Inventor score

Filing activity: Oct 30, 2002 → Dec 15, 2021

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8853785B2	Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuit	Electricity	179	Active
US6855605B2	Semiconductor device with selectable gate thickness and method of manufacturing such devices	Electricity	20	Expired
US10217849B2	Method for making a semiconductor device with nanowire and aligned external and internal spacers	Electricity	6	Active
US10269930B2	Method for producing a semiconductor device with self-aligned internal spacers	Electricity	4	Active
US10431683B2	Method for making a semiconductor device with a compressive stressed channel	Electricity	3	Active
US10217842B2	Method for making a semiconductor device with self-aligned inner spacers	Electricity	3	Active
US10600786B2	Method for fabricating a device with a tensile-strained NMOS transistor and a uniaxial compression strained PMOS transistor	Electricity	2	Active
US9853124B2	Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers	Electricity	2	Active
US9704709B2	Method for causing tensile strain in a semiconductor film	Electricity	2	Active
US10141424B2	Method of producing a channel structure formed from a plurality of strained semiconductor bars	Electricity	2	Active
US9536951B2	FinFET transistor comprising portions of SiGe with a crystal orientation [111]	Electricity	1	Active
US10109735B2	Process for fabricating a field effect transistor having a coating gate	Electricity	1	Active
US8809964B2	Method of adjusting the threshold voltage of a transistor by a buried trapping layer	Electricity	1	Active
US10714392B2	Optimizing junctions of gate all around structures with channel pull back	Electricity	1	Active
US10134875B2	Method for fabricating a transistor having a vertical channel having nano layers	Electricity	1	Active
US11688811B2	Transistor comprising a channel placed under shear strain and fabrication process	Electricity	0	Active
US7879690B2	Method of fabricating a microelectronic structure of a semiconductor on insulator type with different patterns	Electricity	0	Active
US11848191B2	RF substrate structure and method of production	Electricity	0	Active
US11450755B2	Electronic device including at least one nano-object	Electricity	0	Active
US9917153B2	Method for producing a microelectronic device	Electricity	0	Active
US12119258B2	Semiconductor structure comprising a buried porous layer for RF applications	Electricity	0	Active
US10665497B2	Method of manufacturing a structure having one or several strained semiconducting zones that may for transistor channel regions	Electricity	0	Active
US10818775B2	Method for fabricating a field-effect transistor	Electricity	0	Active
US10147788B2	Process for fabricating a field effect transistor having a coating gate	Electricity	0	Active
US10256102B2	Method for fabricating a field effect transistor having a surrounding grid	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.