Process to reduce gate edge drain leakage in semiconductor devices
US6855984B1 · kind B1 · utility
5Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2003 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Oct 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
The present invention employs a no mask, blanket implant of an n-type implant after formation of active regions in NMOS devices. As a result, the implanted n-type dopants counteract portions of strongly p-type HALO or pocket regions creating a smoother dopant profile or transition from a portion of the active regions to the channel. However, the blanket implant is performed at a relatively low energy so as to not significantly alter one or more other portions of the active regions to other portions of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.