Strained-channel multiple-gate transistor
US6855990B2 · kind B2 · utility
183Cited by
10References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2002 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Dec 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/751
Abstract
A multiple-gate semiconductor structure is disclosed which includes a substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces. The fin is subjected to a strain of at least 0.01% and is positioned vertically on the substrate; source and drain regions formed in the semi-conducting material of the fin; a gate dielectric layer overlying the fin; and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces of the fin overlying the gate dielectric layer. A method for forming the multiple-gate semiconductor structure is further disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.