Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies
US6856000B2 · kind B2 · utility
2Cited by
2References
3Claims
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Key dates
| Filing date | Oct 8, 2002 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Oct 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/673
Abstract
An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.