Thin scale outline package
US6856010B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2003 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Jul 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a plurality of vertically stacked semiconductor dies which are electrically connected to each other. Each semiconductor die has leads which extend out from at least two opposed side surfaces of the semiconductor die. Each lead defines a first junction, a second junction, an inner width and an outer width. The second junctions of the leads of the upper semiconductor die are electrically connected to the first junctions of the leads of the lower semiconductor die. Additionally, the inner widths of the leads of the upper semiconductor die prior to electrically connecting the leads of the upper and lower semiconductor dies are less than the outer widths of the leads of the lower semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.