Process independent alignment marks
US6856029B1 · kind B1 · utility
31Cited by
8References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2001 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Jun 22, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit substrate having a first surface for receiving a series of aligned layers during the creation of the integrated circuit, and a second surface disposed substantially opposite the first surface, where the second surface has at least one alignment mark for aligning the series of aligned layers one to another during creation of the integrated circuit. An apparatus for aligning a mask having an image and at least one complimentary alignment mark to a substrate having a first surface and a substantially opposing second surface, where the substrate has at least one alignment mark on the second surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.