Abstract verification environment
US6856950B1 · kind B1 · utility
56Cited by
3References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1999 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Oct 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of verifying an electronic system. A verification kernel is provided and the electronic system is expressed as a logic design. A wrapper is defined, wherein the wrapper is an interface between the logic design and the verification kernel. Tests to be run against the logic design are placed within a diagnostic program and an interface between the diagnostic program and the verification kernel is defined. The tests are then executed against the logic design. The results of the tests are captured and validated against expected results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.