Method and system for triggering a debugging unit
US6857083B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2000 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Nov 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor core for transitioning a debugging unit between a plurality of operating states generates trace data as it processes operating signals of an instruction stream. The processor core provides a trigger event signal to the debugging unit in response to a trigger instruction signal within the instruction stream that is representative of triggering instruction for transitions debugging unit to one of (1) a base operating state, (2) a dynamic storage operating state or (3) a static storage operating state. Concurrently or alternatively, the processor core can provide the trigger event signal to the debugging unit as a function of generated trigger data in response to additional operational instructions within the instruction stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.