Method and apparatus to facilitate self-testing of a system on a chip
US6857092B1 · kind B1 · utility
15Cited by
6References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 25, 2001 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Jul 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318516
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for providing a system-on-a-chip comprising a processor and a configurable system logic (CSL) including a plurality of banks arranged in an array coupled to the processor. The system on a chip further includes a built-in self test (BIST) mechanism coupled to the CSL to perform tests on the CSL to verify that the banks and interconnections between the banks are functioning properly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.