Method for creation of a very narrow emitter feature

US6858485B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Gregory G. Freeman · Hopewell Junction, US
• Marwan H. Khater · New York, US
• Francois Pagette · Fishkill, US
• Andreas D. Stricker · South Burlington, US

Key dates

• Filing date: May 7, 2003
• Grant date: Feb 22, 2005
• Expiry date: May 7, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/133

Abstract

A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped emitter formed in the surface of the intrinsic base. Form an etch stop dielectric layer over the intrinsic base layer above the collector. Form a base contact layer of a conductive material over the etch stop dielectric layer and the intrinsic base layer. Form a second dielectric layer over the base contact layer. Etch a wide window through the dielectric layer and the base contact layer stopping the etching of the window at the etch stop dielectric layer. Form an island or a peninsula narrowing the wide window leaving at least one narrowed window within the wide window. Form sidewall spacers in the either the wide window or the narrowed window. Fill the windows with doped polysilicon to form an extrinsic emitter. Form an emitter below the extrinsic emitter in the surface of the intrinsic base.