Self-aligned dual-floating gate memory cell and method for manufacturing the same
US6858501B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 14, 2003 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Apr 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/687
Abstract
An integrated circuit that includes a first dual-floating gate memory cell having a first floating gate isolated from a second floating gate for storing at least one bit of datum, and a second dual-floating gate memory cell having a third floating gate isolated from a fourth floating gate for storing at least one bit of datum, wherein the first dual-floating gate memory cell and the second dual-floating gate memory cell share a control gate, wherein the second floating gate of the first dual-floating gate memory cell shares an oxide layer with the third floating gate of the second dual-floating gate memory cell, and wherein the oxide layer electrically insulates the second and third floating gates from the control gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.