Patent · US Expired

Ferroelectric memory integrated circuit with improved reliability

US6858890B2 · kind B2 · utility

4Cited by

7References

15Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Michael Jacob · Munich, DE
Uwe Wellhausen · Dresden, DE

Key dates

Filing date	Jun 4, 2002
Grant date	Feb 22, 2005
Priority date	—
Expiry date	Aug 24, 2022

Classification

Technology area (CPC H)Electricity
CPC primaryH10B53/30
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An IC with memory cells arranged in a chained architecture is disclosed. The top local interconnect between the top capacitor electrodes and active area is achieved by using a strap. The use of a strap eliminates the need for additional metal layer which reduces manufacturing costs. Furthermore, sidewall spacers are used to isolate the strap from the different layers of the capacitors. The use of spacers advantageously enables the strap to be self-aligned.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.