Device and method for measuring jitter in phase locked loops
US6859027B2 · kind B2 · utility
5Cited by
8References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 15, 2002 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Aug 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device and method for measuring the jitters of phase locked loop signals. A phase lead or phase lag relationship between an input signal and an output signal of a phase locked loop is found. According to the phase relationship and using multiplexers, a first phase difference signal and a second phase difference signal are re-routed to a subtraction unit and produces a jitter-level output signal. The jitter-level output signal represents the absolute value of the difference of pulse width between the first phase difference signal and the second phase difference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.