Duty cycle correction circuit and delay locked loop having the same
US6859081B2 · kind B2 · utility
52Cited by
13References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2003 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Aug 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle correction (DCC) circuit including first and second clock dividers for dividing ordinary and sub-input clocks. Optional first and second variable delay devices delay the divided clocks. First and second mixers mix an optionally delayed ordinary divided clock and sub-ordinary divided clock, or an ordinary divided clock and an optionally delayed sub-ordinary divided clock. A logic combination device is included to produce a clock at the same frequency as the ordinary and sub-input clocks, with a corrected duty cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.