NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages
US6859395B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2003 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Apr 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device includes a NAND memory cell array, booster circuit, row decoder, bit line control circuit and column decoder. In the device, the magnitude of intermediate voltage applied to the control gates of memory transistors from the booster circuit via the row decoder is changed according to the position of a selected control gate line when data is sequentially programmed into the memory transistors in the memory cell array. Alternatively, a plurality of different intermediate voltages are applied when data is simultaneously programmed into memory transistors connected to the selected control gate line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.