Method and apparatus for software management of on-chip cache
US6859862B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2000 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Apr 7, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor including a control unit and a cache connected with the control unit for storing data to be used by the control, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion. The normal cache portion is controlled by a hardware implemented automatic replacement process. The locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache. An instruction is provided in the instruction set that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory, thereby enabling the locked cache portion to be completely managed by software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.