Method and apparatus for reducing power consumption in a pipelined processor
US6859871B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1998 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Mar 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides techniques for reducing the power consumption of pipelined processors. In an illustrative embodiment, the invention evaluates the predicates of predicated instructions in a decode stage of a pipelined processor, and annuls instructions with false predicates before those instructions can be processed by subsequent stages, e.g, by execute and writeback stages. The predicate dependencies can be handled using, e.g., a virtual single-cycle execution technique which locks a predicate register while the register is in use by a given instruction, and then stalls subsequent instructions that depend on a value stored in the register until the register is unlocked. As another example, the predicate dependencies can be handled using a compiler-controlled dynamic dispatch (CCDD) technique, which identifies dependencies associated with a set of instructions during compilation of the instructions in a compiler. One or more instructions are then grouped in a code block which includes a field indicating the dependencies associated with those instructions, and the instructions are then, e.g., either stalled or decoded serially, based on the dependencies present in the code blo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.