Signal line impedance verification tool
US6859915B1 · kind B1 · utility
14Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2003 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Aug 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/0005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method for verifying impedance of a signal line in an electrical circuit layout includes reading a desired impedance value for a signal line and identifying the signal line in a circuit design database. A window is established around the signal line in which circuit elements will be included in an impedance calculation for the signal line. The impedance of the signal line is calculated based on the circuit elements inside the window. The signal line is flagged if the calculated impedance differs from the desired impedance value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.