Semiconductor structure having an improved pre-metal dielectric stack and method for forming the same
US6861352B2 · kind B2 · utility
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18References
19Claims
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Key dates
| Filing date | Dec 22, 2003 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Dec 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31051
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a substrate, a dielectric layer disposed on the substrate, a layer of undoped silicate glass disposed on the dielectric layer, a layer of borophosphorous silicate glass on the layer of undoped silicate glass, and a planar dielectric layer disposed on the layer of borophosphorous silicate glass, the layers of undoped silicate glass, borophosphorous silicate glass, and planar dielectric together forming a pre-metal dielectric stack. The planar dielectric may include plasma-enhanced tetraethyl orthosilicate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.