Semiconductor device having multi-layer wiring
US6861670B1 · kind B1 · utility
132Cited by
16References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2000 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Mar 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6743
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The object is to pattern extremely fine integrated circuits by forming fine contact holes. The dry etching method is employed to form contact holes to pattern a wiring (114), using a mask made of metallic film (112) and an organic material as an inter-layer insulating film (111) for covering switching elements and each of the wirings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.