Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor
US6861684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2002 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Jul 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/66
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The vertical transistor includes, on a semiconductor substrate, a vertical pillar 5 having one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielectric layer 7 situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The gate includes a semiconductor block having a first region 800 resting on the gate dielectric layer 7 and a second region 90 facing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavities 14S, 14D.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.