Method of manufacturing semiconductor device and semiconductor device
US6861692B2 · kind B2 · utility
5Cited by
3References
8Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jan 8, 2003 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Jan 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/047
Abstract
A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.