Trench power MOSFET with planarized gate bus
US6861701B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 5, 2003 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Apr 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/664
Abstract
Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The conductive gate structure forms gates in device trenches in an active device region and forms a gate bus in a gate bus trench. The gate bus trench that connects to the device trenches can be wide to facilitate forming a gate contact to the gate bus, while the device trenches can be narrow to maximize device density. CMP process can be used to planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.