MOSFET threshold voltage tuning with metal gate stack control
US6861712B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2003 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Jan 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked metal gate MOSFET and fabrication method are provided. The method comprises: forming a gate oxide layer overlying a channel region; forming a first metal layer having a first thickness overlying the gate oxide layer; forming a second metal layer having a second thickness overlying the first metal layer; and, establishing a gate work function in response to the combination of the first and second thicknesses. In one example, the first metal layer has a thickness of less than about 1.5 nanometers (nm) the second metal layer has a thickness greater than about 10 nm. Then, establishing a gate work function includes establishing a gate work function substantially in response to the second metal second thickness. Alternately, the first metal thickness is greater than about 20 nm. Then, the gate work function is established substantially in response to the first metal thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.