Method and apparatus for built-in self-test of logic circuits with multiple clock domains
US6861867B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2002 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Jun 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318594
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for remotely/automatedly testing an ASIC and particularly to testing a user-designed circuit is disclosed. In general, a system in accordance with the invention includes a plurality of cells, where the cells are couplable to form a user-designed circuit, e.g., by customizing routing. Within the ASIC and prior to any knowledge of the user-designed circuit, the ASIC includes circuitry to enable internal remote/automated testing of the user-designed circuit to be later formed. The circuitry controls the input and mode of operation of the cells and the sequencing of multiple synchronous or asynchronous clock domain inputs thereby providing testing of the user-designed circuit at speed for stuck-at-faults and delay faults.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.