Circuit to independently adjust rise and fall edge timing of a signal
US6861877B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 17, 2003 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Mar 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/133
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit to independently control rise and fall delay edge timing of a signal is achieved. The circuit comprises, first, a first delay element and a second delay element. Each of the delay elements has an input and an output. Each of the inputs is coupled to a common, input signal. Next, an AND function, having two inputs and one output, is used. One of the AND inputs is coupled to the input signal, and another of the AND inputs is coupled to the first delay element output. The AND function output comprises a rise-delayed signal having a controlled rising edge delay between a rising edge of the input signal and a rising edge of the rise-delay signal. Finally, an OR function, having two inputs and one output, is used. One of the OR inputs is coupled to the input signal, and another of the OR inputs is coupled to the second delay element output. The OR function output comprises a fall-delayed signal having a controlled falling edge delay between a falling edge of the input signal and a falling edge of the fall-delay signal. A means of combining the rise-delayed signal and the fall-delayed signal into a common, delayed output signal is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.