Semiconductor memory device having the operating voltage of the memory cell controlled
US6862227B2 · kind B2 · utility
12Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 2003 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | May 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM circuit which can be operated at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operating voltage of a memory cell with the operating voltage of a peripheral circuit in order to adjust it to the optimum value, and the substrate bias voltage is further controlled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.