First tier cache memory preventing stale data storage
US6862669B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2002 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Feb 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/822
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a compute engine coupled to a first tier cache memory including a data array. The first tier cache receives memory access requests from the compute engine. A second tier cache memory is coupled to the first tier cache to receive memory access requests for memory locations not owned by the first tier cache. To avoid stale data storage, the first tier cache does not load the data array with data returned by the second tier cache under the following condition—the second tier cache returns the data in response to a cacheable load operation from a memory location after the compute engine issues a subsequent store operation to the same memory location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.