David T. Hass
57Patents
20h-index
32Co-inventors
84Inventor score
Filing activity: Dec 31, 1998 → Oct 17, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6880049B2 | Sharing a second tier cache memory in a multi-processor | Electricity | 121 | Expired |
| US7765328B2 | Content service aggregation system | Electricity | 92 | Active |
| US7305492B2 | Content service aggregation system | Electricity | 89 | Expired |
| US7334086B2 | Advanced processor with system on a chip interconnect technology | Physics | 60 | Expired |
| US7627721B2 | Advanced processor with cache coherency | Physics | 30 | Expired |
| US7467243B2 | Advanced processor with scheme for optimal packet flow in a multi-processor system on a chip | Physics | 30 | Expired |
| US7346757B2 | Advanced processor translation lookaside buffer management in a multithreaded system | Physics | 29 | Expired |
| US6591359B1 | Speculative renaming of data-processor registers | Physics | 28 | Expired |
| US7461213B2 | Advanced processor system using request, data, snoop, and response rings | Physics | 28 | Expired |
| US6895477B2 | Ring-based memory requests in a shared memory multi-processor | Electricity | 26 | Expired |
| US8370528B2 | Content service aggregation system | Electricity | 26 | Active |
| US7461215B2 | Advanced processor with implementation of memory ordering on a ring based data movement network | Electricity | 26 | Expired |
| US6901482B2 | Managing ownership of a full cache line using a store-create operation | Electricity | 25 | Expired |
| US7509476B2 | Advanced processor translation lookaside buffer management in a multithreaded system | Physics | 23 | Active |
| US8015567B2 | Advanced processor with mechanism for packet distribution at high line rate | Physics | 21 | Active |
| US8754681B2 | Multi-part clock management | Electricity | 21 | Active |
| US7995596B2 | System and method for offloading packet protocol encapsulation from software | Electricity | 21 | Active |
| US7509462B2 | Advanced processor with use of bridges on a data movement ring for optimal redirection of memory and I/O traffic | Physics | 21 | Expired |
| US6839808B2 | Processing cluster having multiple compute engines and shared tier one caches | Electricity | 20 | Expired |
| US7627717B2 | Advanced processor messaging apparatus including fast messaging ring components configured to accomodate point-to-point transfer of non-memory related messages | Physics | 20 | Active |
| US7538695B2 | System and method for deflate processing within a compression engine | Electricity | 17 | Active |
| US8499302B2 | Advanced processor with mechanism for packet distribution at high line rate | Physics | 16 | Active |
| US7538696B2 | System and method for Huffman decoding within a compression engine | Electricity | 13 | Active |
| US6892282B2 | Ring based multi-processing system | Electricity | 13 | Expired |
| US8438337B1 | System and method for conditionally sending a request for data to a home node | Physics | 13 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.