Method for identification of faulty or weak functional logic elements under simulated extreme operating conditions
US6862721B2 · kind B2 · utility
4Cited by
5References
18Claims
0Family size
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Key dates
| Filing date | Sep 17, 2003 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Sep 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for testing a circuit is provided. The method includes providing a normal internal clock signal for use in accessing functional logic, where the functional logic has access to redundant functional logic during normal operation. The method then applies a stress clock signal to the functional logic, and each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal. Based on the applied stress clock signal, the method identifies logic elements of the functional logic that fail to operate as intended.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.