Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching

US6864041B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jeffrey J. Brown · Palmyra, US
• Sadanand V. Deshpande · Fishkill, US
• David V. Horak · South Burlington, US
• Maheswaran Surendra · Croton-on-Hudson, US
• Len Yuan Tsou · New City, US
• Qingyun Yang · Hopewell Junction, US
• Chienfan Yu · Highland Mills, US
• Ying Zhang · Santa Clara, US

Key dates

• Filing date: May 2, 2001
• Grant date: Mar 8, 2005
• Expiry date: Oct 10, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G03F7/427
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.