Patent · US Expired

Compact semiconductor structure

US6864170B2 · kind B2 · utility

0Cited by

8References

3Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Falko Höhnsdorf · Dresden, DE
Albrecht Kieslich · Radebeul, DE
Detlef Weber · Grünberg, DE

Key dates

Filing date	Nov 28, 2001
Grant date	Mar 8, 2005
Priority date	—
Expiry date	Nov 28, 2021

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for reducing capacitative coupling between interconnects on a semiconductor structure includes producing a first insulating layer on a semiconductor substrate and etching trenches in the first insulating layer. Metallic interconnects are formed in the trenches by metallization. The semiconductor structure is polished to remove metal from the first insulating layer, leaving behind metal in the trenches. A portion of the first insulating layer between the first and second metallic interconnects is etched so that the first and second metallic interconnects project above the first insulating layer. A second insulating layer is applied on the substrate such that the metallic interconnects project into the second insulating layer. The second insulating layer has a relative permittivity that is lower than the relative permittivity of the first insulating layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.