Semiconductor wafer
US6864534B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2001 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Aug 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/405
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To provide a semiconductor wafer having crystal orientations of a wafer for the support substrate and a wafer for the device formation shifted from each other, wherein two kinds of wafers having different crystal orientations in which a notch or an orientation flat is to be provided do not need to be prepared. One of two semiconductor wafers having a notch or an orientation flat provided in the same crystal orientation <110> is set to be a wafer (1) for the support substrate and the other is set to be a wafer for the device formation. Both wafers are bonded with the notches or orientation flats shifted from each other (for example, a crystal orientation <100> of the wafer for the device formation and the crystal orientation <110> of the wafer (1) for the support substrate are set to the same direction). The wafer for the device formation is divided to obtain an SOI layer (3). A MOS transistor (TR1) or the like is formed on the SOI layer (3).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.