High performance FET with elevated source/drain region

US6864540B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Rama Divakaruni · Ossining, US
• Louis C. Hsu · Fishkill, US
• Rajiv V. Joshi · Yorktown Heights, US
• Carl Radens · Lagrangeville, US

Key dates

• Filing date: May 21, 2004
• Grant date: Mar 8, 2005
• Expiry date: May 21, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212

Abstract

The invention includes a field effect transistor (FET) on an insulator layer, and integrated circuit (IC) on SOI chip including the FETs and a method of forming the IC. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.