Bipolar transistor structure with a shallow isolation extension region providing reduced parasitic capacitance

US6864560B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Marwan H. Khater · New York, US
• Jae-Sung Rieh · Seoul, KR
• Andreas D. Stricker · South Burlington, US
• Gregory G. Freeman · Hopewell Junction, US
• Kathryn T. Schonenberg · Wappingers Falls, US

Key dates

• Filing date: Mar 28, 2003
• Grant date: Mar 8, 2005
• Expiry date: Mar 28, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/115

Abstract

A bipolar vertical transistor is formed in a silicon semiconductor substrate which has an upper surface with STI regions formed therein composed of a dielectric material formed in the substrate having inner ends and top surfaces. A doped collector region is formed in the substrate between a pair of the STI regions. A counterdoped intrinsic base region is formed on the upper surface of the substrate between the pair of the STI regions with a margin between the intrinsic base region and the pair of STI regions, the intrinsic base region having edges. A doped emitter region is formed above the intrinsic base region spaced away from the edges. A shallow isolation extension region composed of a dielectric material is next to the edges of the intrinsic base region formed in the margin between the STI regions and the intrinsic base region. An extrinsic base region covers the shallow isolation extension region and extends partially over the intrinsic base region in mechanical and electrical contact therewith, whereby the shallow isolation extension region reduces the base-to-collector parasitic capacitance of the bipolar transistor.