PLDs providing reduced delays in cascade chain circuits

US6864714B2 · kind B2 · utility

Assignee

• STMICROELECTRONICS, INC. · US

Inventors

• Kailash Digari · Noida, IN
• Nitin Deshmukh · Mumbai, IN

Key dates

• Filing date: Jun 10, 2003
• Grant date: Mar 8, 2005
• Expiry date: Aug 17, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/17728
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

The present invention provides a Programmable Logic Device (PLD) incorporating a two-input multiplexer for providing a Cascade Logic output and having a Cascade Logic input coupled to a select line. A two-input multiplexer provides the desired configurable Cascade Logic function, and an initialization circuit sets the initial value for the Cascade logic under control of an initialization configuration bit. The multiplexer that provides the Cascade Logic output also provides the desired configurable Cascade Logic function using the Look-up table (LUT) and configuration bits.