Windowing circuit for aligning data and clock signals
US6864715B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2003 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Feb 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Described are circuits and methods for aligning data and clock signals. Circuits in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.