Frequency multiplier and amplification circuit
US6864728B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2003 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Feb 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency multiplier and amplification circuit are disclosed. One embodiment of the present invention comprises: a multiplier operably coupled to multiply a first sinusoidal waveform having a first frequency with a second sinusoidal waveform having a second frequency to produce a third sinusoidal waveform, having a frequency representative of a difference between the first frequency and the second frequency, and a fourth sinusoidal waveform having a frequency representative of a sum of the first and second frequencies; and a frequency-tuned load operably coupled to substantially attenuate the third sinusoidal waveform and to substantially pass the fourth sinusoidal waveform as an output of the frequency-tuned multiplier circuit. The frequency-tuned multiplier circuit can be a single-ended multiplier circuit or a differential multiplier circuit with corresponding single-ended or differential first and second sinusoidal waveforms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.