Program store compare handling between instruction and operand caches
US6865645B1 · kind B1 · utility
16Cited by
7References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2000 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Aug 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of supporting programs that include instructions that modify subsequent instructions in a multi-processor system with a central processing unit including an execution unit, and instruction unit and a plurality of caches including a separate instruction and operand cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.