CPU-based system and method for testing embedded memory
US6865694B2 · kind B2 · utility
2Cited by
14References
10Claims
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Key dates
| Filing date | Apr 30, 2002 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Sep 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CPU-based system 10 and method for testing embedded memory. The technique employs the on-chip CPU 20 itself to test the embedded memory 24. An assembly code program is loaded into the device under test (DUT) 12 to test the memories, determine a repair solution, and write out the repair solution and raw failure information to the tester for defect analysis. The test is driven by an external programmable clock that is provided by the tester to allow the DUT 12 to run up to its maximum input clock rate in order to maximize throughput. The test is not dependent on the pattern rate of the tester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.