Semiconductor process using delay-compensated exposure
US6866974B2 · kind B2 · utility
13Cited by
1References
7Claims
0Family size
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Key dates
| Filing date | Oct 21, 2002 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Sep 6, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70425
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of providing critical dimension (CD) gate control during photolithography is achieved by scanning a trial wafer from a batch by an exposure tool and then measuring the gate width to determine shot zones for bi-shot (BSE) exposure. The time delay based on shot or exposure order is determined for each BSE zone. The shot or exposure dose for the other wafers from the same or similar batch is then determined on the bi-shot exposure and the shot order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.