Package for integrated circuit die
US6867367B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 29, 2004 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Jan 29, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24132
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit package for housing semiconductor or other integrated circuit devices (“die”) includes a high-copper flange, one or more high-copper leads and a liquid crystal polymer frame molded to the flange and the leads. The flange includes a dovetail-shaped groove or other frame retention feature that mechanically interlocks with the molded frame. During molding, a portion of the frame forms a key that freezes in or around the frame retention feature. The leads include one or more lead retention features to mechanically interlock with the frame. During molding, a portion of the frame freezes in or adjacent these lead retention features. The frame includes compounds to prevent moisture infiltration and match its coefficient of thermal expansion (CTE) to the CTE of the leads and flange. The is frame is formulated to withstand die-attach temperatures. A lid is ultrasonically welded to the frame after a die is attached to the flange.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.