Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

US6867433B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Yee-Chia Yeo · Baoshan, TW
• How-Yu Chen
• Chien-Chao Huang · Baoshan, TW
• Wen-Chin Lee · Baoshan, TW
• Fu-Liang Yang · Baoshan, TW
• Chenming Hu · Alamo, US

Key dates

• Filing date: Apr 30, 2003
• Grant date: Mar 15, 2005
• Expiry date: Apr 30, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.