Read only memory configuration to reduce capacitance effect between numbers of bit lines
US6867995B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2003 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Jun 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read only memory device includes multiple word lines, a first and second main bit line GL (n) and BL (n), sub-bit lines SB1 (n) to SB4 (n), selection switches MB1 (n) to MB4 (n), and memory cells M1 (n) to M4 (n). The memory cells M1 (n) to M4 (n) are electrically coupled to the sub-bit lines SB1 (n) to SB4 (n) and the sub-bit line SB1 (n+1), respectively. When the memory cell M3 (n) which is connected to SB3 (n) is read, the sub-bit lines SB1 (n) to SB3 (n) are connected to the corresponding main bit lines through the turned selection switches. At this time, the sub-bit lines SB1 (n) to SB3 (n) are not floating but are all at the same high voltage level. Therefore, the capacitance effect will not exist between them to change the voltage level of the sub-bit lines quickly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.