Circuit and method for processing data
US6868431B1 · kind B1 · utility
3Cited by
11References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1999 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Oct 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Finite Impulse Response (FIR) filter circuit (60) includes delay elements (63, 64, 66), multipliers (71, 72, 73, 74), a summing device (78), and a digital integrator (69) at the output of the FIR filter circuit (60). A method for processing data using the FIR filter circuit (60) includes differentially encoding data prior to storing or processing of the data. The method provides a technique for compressing data since less memory is needed to store derivative data. The method further includes integrating the derivative data using the digital integrator (69) to decompress the derivative data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.