Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory
US6868472B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2000 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Sep 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2515
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.