Computer system with integrated directory and processor cache
US6868485B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2002 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Mar 15, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system with an integrated directory and processor cache. Directory entries are maintained to filter probe command and response traffic for certain coherent transactions. Rather than storing directory entries in a dedicated directory storage, directory entries may be stored in designated locations of cache memory subsystem, such as an L2 cache, associated with a processor core. In one particular implementation, directory entries are stored within the cache memory subsystem to provide indications of lines (or blocks) that may be cached in modified, exclusive, or owned coherency states. The absence of a directory entry for a particular line may imply that the line is cached in either shared or invalid states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.