Patent · US Expired

Filling high aspect ratio isolation structures with polysilazane based material

US6869860B2 · kind B2 · utility

18Cited by
16References
10Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 3, 2003
Grant dateMar 22, 2005
Priority date
Expiry dateJun 3, 2023

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/76229
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H2O ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.