Silicide proximity structures for CMOS device performance improvements
US6869866B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2003 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Sep 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A method for manufacturing an integrated circuit having a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor on a semiconductor wafer by creating a spacer having a first width for the n-type field effect transistor and creating a spacer having a second width for the p-type field effect transistor, the first width being greater than the second width and depositing silicide material on the semiconductor wafer such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor and compressive stresses are formed within a channel of the p-type field effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.